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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>LD2 (multiple structures) -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">LD2 (multiple structures)</h2>
      <p class="aml">Load multiple 2-element structures to two registers. This instruction loads multiple 2-element structures from memory and writes the result to the two SIMD&amp;FP registers, with de-interleaving.</p>
      <p class="aml">For an example of de-interleaving, see <span class="asm-code">LD3 (multiple structures)</span>.</p>
      <p class="aml">Depending on the settings in the <a class="armarm-xref" title="Reference to Armv8 ARM section">CPACR_EL1</a>, <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL2</a>, and <a class="armarm-xref" title="Reference to Armv8 ARM section">CPTR_EL3</a> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</p>
    
    <p class="desc">
      It has encodings from 2 classes:
      <a href="#iclass_as_no_post_index">No offset</a>
       and 
      <a href="#iclass_as_post_index">Post-index</a>
    </p>
    <h3 class="classheading"><a id="iclass_as_no_post_index"/>No offset</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">Q</td><td class="l">0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="l">1</td><td>0</td><td>0</td><td class="r">0</td><td colspan="2" class="lr">size</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td/><td/><td colspan="7"/><td class="droppedname">L</td><td colspan="6"/><td colspan="4" class="droppedname">opcode</td><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="LD2_asisdlse_R2"/><p class="asm-code">LD2  { <a href="#sa_vt" title="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;size:Q&quot;) [2D,2S,4H,4S,8B,8H,16B]">&lt;T&gt;</a>, <a href="#sa_vt2" title="Second SIMD&amp;FP register to be transferred (field Rt)">&lt;Vt2&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;size:Q&quot;) [2D,2S,4H,4S,8B,8H,16B]">&lt;T&gt;</a> }, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>]</p></div><p class="pseudocode">integer t = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rt);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = integer UNKNOWN;
boolean wback = FALSE;
boolean nontemporal = FALSE;
boolean tagchecked = wback || n != 31;</p>
    <h3 class="classheading"><a id="iclass_as_post_index"/>Post-index</h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="lr">Q</td><td class="l">0</td><td>0</td><td>1</td><td>1</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="lr">0</td><td colspan="5" class="lr">Rm</td><td class="l">1</td><td>0</td><td>0</td><td class="r">0</td><td colspan="2" class="lr">size</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rt</td></tr><tr class="secondrow"><td/><td/><td colspan="7"/><td class="droppedname">L</td><td/><td colspan="5"/><td colspan="4" class="droppedname">opcode</td><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">Immediate offset<span class="bitdiff"> (Rm == 11111)</span></h4><a id="LD2_asisdlsep_I2_i"/><p class="asm-code">LD2  { <a href="#sa_vt" title="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;size:Q&quot;) [2D,2S,4H,4S,8B,8H,16B]">&lt;T&gt;</a>, <a href="#sa_vt2" title="Second SIMD&amp;FP register to be transferred (field Rt)">&lt;Vt2&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;size:Q&quot;) [2D,2S,4H,4S,8B,8H,16B]">&lt;T&gt;</a> }, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>], <a href="#sa_imm" title="Post-index immediate offset (field &quot;Q&quot;) [#16,#32]">&lt;imm&gt;</a></p></div><div class="encoding"><h4 class="encoding">Register offset<span class="bitdiff"> (Rm != 11111)</span></h4><a id="LD2_asisdlsep_R2_r"/><p class="asm-code">LD2  { <a href="#sa_vt" title="First or only SIMD&amp;FP register to be transferred (field &quot;Rt&quot;)">&lt;Vt&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;size:Q&quot;) [2D,2S,4H,4S,8B,8H,16B]">&lt;T&gt;</a>, <a href="#sa_vt2" title="Second SIMD&amp;FP register to be transferred (field Rt)">&lt;Vt2&gt;</a>.<a href="#sa_t" title="Arrangement specifier (field &quot;size:Q&quot;) [2D,2S,4H,4S,8B,8H,16B]">&lt;T&gt;</a> }, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field &quot;Rn&quot;)">&lt;Xn|SP&gt;</a>], <a href="#sa_xm" title="64-bit general-purpose post-index register, excluding XZR (field &quot;Rm&quot;)">&lt;Xm&gt;</a></p></div><p class="pseudocode">integer t = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rt);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);
boolean wback = TRUE;
boolean nontemporal = FALSE;
boolean tagchecked = wback || n != 31;</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vt&gt;</td><td><a id="sa_vt"/>
        
          <p class="aml">Is the name of the first or only SIMD&amp;FP register to be transferred, encoded in the "Rt" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;T&gt;</td><td><a id="sa_t"/>
        <p>Is an arrangement specifier, 
      encoded in
      <q>size:Q</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">size</th>
                <th class="bitfield">Q</th>
                <th class="symbol">&lt;T&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">00</td>
                <td class="bitfield">0</td>
                <td class="symbol">8B</td>
              </tr>
              <tr>
                <td class="bitfield">00</td>
                <td class="bitfield">1</td>
                <td class="symbol">16B</td>
              </tr>
              <tr>
                <td class="bitfield">01</td>
                <td class="bitfield">0</td>
                <td class="symbol">4H</td>
              </tr>
              <tr>
                <td class="bitfield">01</td>
                <td class="bitfield">1</td>
                <td class="symbol">8H</td>
              </tr>
              <tr>
                <td class="bitfield">10</td>
                <td class="bitfield">0</td>
                <td class="symbol">2S</td>
              </tr>
              <tr>
                <td class="bitfield">10</td>
                <td class="bitfield">1</td>
                <td class="symbol">4S</td>
              </tr>
              <tr>
                <td class="bitfield">11</td>
                <td class="bitfield">0</td>
                <td class="symbol">RESERVED</td>
              </tr>
              <tr>
                <td class="bitfield">11</td>
                <td class="bitfield">1</td>
                <td class="symbol">2D</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Vt2&gt;</td><td><a id="sa_vt2"/>
        
          <p class="aml">Is the name of the second SIMD&amp;FP register to be transferred, encoded as "Rt" plus 1 modulo 32.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xn|SP&gt;</td><td><a id="sa_xn_sp"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;imm&gt;</td><td><a id="sa_imm"/>
        <p>Is the post-index immediate offset, 
      encoded in
      <q>Q</q>:
        </p>
        <table class="valuetable">
          
            <thead>
              <tr>
                <th class="bitfield">Q</th>
                <th class="symbol">&lt;imm&gt;</th>
              </tr>
            </thead>
            <tbody>
              <tr>
                <td class="bitfield">0</td>
                <td class="symbol">#16</td>
              </tr>
              <tr>
                <td class="bitfield">1</td>
                <td class="symbol">#32</td>
              </tr>
            </tbody>
          
        </table>
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xm&gt;</td><td><a id="sa_xm"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="postdecode"/><h3 class="pseudocode">Shared Decode</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#MemOp" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp</a> memop = if L == '1' then <a href="shared_pseudocode.html#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> else <a href="shared_pseudocode.html#MemOp_STORE" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_STORE</a>;
integer datasize = if Q == '1' then 128 else 64;
integer esize = 8 &lt;&lt; <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
integer elements = datasize DIV esize;

integer rpt;    // number of iterations
integer selem;    // structure elements

case opcode of
    when '0000' rpt = 1; selem = 4;    // LD/ST4 (4 registers)
    when '0010' rpt = 4; selem = 1;    // LD/ST1 (4 registers)
    when '0100' rpt = 1; selem = 3;    // LD/ST3 (3 registers)
    when '0110' rpt = 3; selem = 1;    // LD/ST1 (3 registers)
    when '0111' rpt = 1; selem = 1;    // LD/ST1 (1 register)
    when '1000' rpt = 1; selem = 2;    // LD/ST2 (2 registers)
    when '1010' rpt = 2; selem = 1;    // LD/ST1 (2 registers)
    otherwise UNDEFINED;

// .1D format only permitted with LD1 &amp; ST1
if size:Q == '110' &amp;&amp; selem != 1 then UNDEFINED;</p>
    </div>
  
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckFPAdvSIMDEnabled64.0" title="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();

bits(64) address;
bits(64) offs;
bits(datasize) rval;
integer tt;
constant integer ebytes = esize DIV 8;

<a href="shared_pseudocode.html#AccessDescriptor" title="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a href="shared_pseudocode.html#impl-shared.CreateAccDescASIMD.3" title="function: AccessDescriptor CreateAccDescASIMD(MemOp memop, boolean nontemporal, boolean tagchecked)">CreateAccDescASIMD</a>(memop, nontemporal, tagchecked);
if n == 31 then
    <a href="shared_pseudocode.html#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
    address = <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[];
else
    address = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

offs = <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(64);
for r = 0 to rpt-1
    for e = 0 to elements-1
        tt = (t + r) MOD 32;
        for s = 0 to selem-1
            rval = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[tt, datasize];
            if memop == <a href="shared_pseudocode.html#MemOp_LOAD" title="enumeration MemOp {MemOp_LOAD, MemOp_STORE, MemOp_PREFETCH}">MemOp_LOAD</a> then
                <a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[rval, e, esize] = <a href="shared_pseudocode.html#impl-aarch64.Mem.read.3" title="accessor: bits(size*8) Mem[bits(64) address, integer size, AccessDescriptor accdesc]">Mem</a>[address+offs, ebytes, accdesc];
                <a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[tt, datasize] = rval;
            else // memop == MemOp_STORE
                <a href="shared_pseudocode.html#impl-aarch64.Mem.write.3" title="accessor: Mem[bits(64) address, integer size, AccessDescriptor accdesc] = bits(size*8) value_in">Mem</a>[address+offs, ebytes, accdesc] = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[rval, e, esize];
            offs = offs + ebytes;
            tt = (tt + 1) MOD 32;

if wback then
    if m != 31 then
        offs = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[m, 64];
    if n == 31 then
        <a href="shared_pseudocode.html#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(64) value">SP</a>[] = address + offs;
    else
        <a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[n, 64] = address + offs;</p>
    </div>
  <h3>Operational information</h3>
    <p class="aml">If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.</p>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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